The simulation of SystemVerilog language is based on a discrete event execution model.
Processes can be evaluated and have their own state. They are concurrently scheduled. They are sensitive to update events.
Every change of a net or a variable generates an event (update event). An evaluation of a process also generates an event (evaluation event).
Except events the important aspect of the simulation is the simulation time. It is the time value which is maintained by the simulator to model the actual time in the design being simulated.
The simples simulation time unit is named time slot. The time slot is divided into several regions, in which events can be scheduled. In the appropriate regions of a time slot different kinds of events are executed.
The dividing a time slot into ordered regions helps to provide predictable interactions between the design and testbench code.
Regions Observed, Reactive and Re-inactive regions are new regions according to the IEEE 1364 model. Rest of regions corresponds to IEEE 1364 simulation model.
In the Observed region evaluation of property expressions is executed.
The pass/fail code from the assertion/cover actions block is scheduled in the Reactive region of the current time slot.
The sampling of signals used in sequences and properties expressions is executed in Preponed region. The sampling of signals with #1step input skew (see Clocking Blocks chapter) is also executed in the Preponed region.
A #0 control delay specified in a program block schedules the process for resumption in the Re-inactive region.