SystemVerilog Language Reference Manual (LRM)

IEEE 1800^TM SystemVerilog is the industry's first unified hardware description and verification language (HDVL) standard. SystemVerilog is a major extension of the established IEEE 1364^TM Verilog language. It was developed originally by Accellera to dramatically improve productivity in the design of large gate-count, IP-based, bus-intensive chips. It specifies the Accellera extensions for a higher level of abstraction for modeling and verification with the Verilog Hardware Description Language. These additions extend Verilog into the systems space and the verification space.

SystemVerilog is targeted primarily at the chip implementation and verification flow, with powerful links to the system-level design flow. SystemVerilog has been adopted by 100's of semiconductor design companies and supported by more than 75 EDA, IP and training solutions worldwide.

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SystemVerilog Keywords

black - keywords existing in Verilog standard
blue - SystemVerilog keywords

alias always always_comb always_ff always_latch and assert assign assume automatic before begin bind bins binsof bit break buf bufif0 bufif1 byte case casex casez cell chandle class clocking cmos config const constraint context continue cover covergroup coverpoint cross deassign default defparam design disable dist do edge else end endcase endclass endclocking endconfig endfunction endgenerate endgroup

endinterface endmodule endpackage endprimitive endprogram endproperty endspecify endsequence endtable endtask enum event expect export extends extern final first_match for force foreach forever fork forkjoin function generate genvar highz0 highz1 if iff ifnone ignore_bins illegal_bins import incdir include initial inout input inside instance int integer interface intersect join join_any join_none large liblist library local localparam logic

longint macromodule matches medium modport module nand negedge new nmos nor noshowcancelled not notif0 notif1 null or output package packed parameter pmos posedge primitive priority program property protected pull0 pull1 pulldown pullup pulsestyle_onevent pulsestyle_ondetect pure rand randc randcase randsequence rcmos real realtime ref reg release repeat return rnmos rpmos rtran rtranif0 rtranif1 scalared sequence shortint

shortreal showcancelled signed small solve specify specparam static string strong0 strong1 struct super supply0 supply1 table tagged task this throughout time timeprecision timeunit tran tranif0 tranif1 tri tri0 tri1 triand trior trireg type typedef union unique unsigned use uwire var vectored virtual void wait wait_order wand weak0 weak1 while wildcard wire with within wor xnor xor

Introduction to SystemVerilog

Verilog 1995 version has been in market for a very long time. IEEE extended the features of Verilog 1995 and released it as Verilog 2001. But this was no good for verification engineers, so verification engineers had to use languages like "e", VERA, Testbuider. It was rather painfull to have two languages, one for design and other for verification. SystemVerilog combines the Verification capabilities of HVL (Hardware Verification Language) with ease of Verilog to provide a single platform for both design and verification.

Some of the new features in SystemVerilog are as listed below.

• C type data types like int, typedef, struct, union, enum.
• Dynamic data types: struct, classes, dynamic queues, dynamic arrays.
• New operators and built in methods.
• Enhanced flow control like, foreach, return, break and continue.
• Semaphores, mailboxes, event extensions.
• Classes for object oriented programming.
• Assertions.
• Coverage.
• VPI extensions.

Now IEEE has accepted the SystemVerilog and it will be official integrated into Verilog 2005, which is suppose to be released in year 2005.

Anyone with background of C++, or OO programming language will feel at home with SystemVerilog. But on other hand if you have been thinking C or C++ is not required, then you may be shocked to know that SystemVerilog is very much like C++.

This document specifies the Accellera extensions for a higher level of abstraction for modeling and verification with the Verilog Hardware Description Language. These additions extend Verilog into the systems space and the verification space. SystemVerilog is built on top of the work of the IEEE Verilog 2001 committee.

Throughout this document:

• “Verilog” or “Verilog-2001” refers to the IEEE Std. 1364-2001 standard for the Verilog Hardware Description Language

• “SystemVerilog” refers to the Accellera extensions to the Verilog-2001 standard.

• This document numbers the generations of Verilog as follows:

• “Verilog 1.0” is the IEEE Std. 1364-1995 Verilog standard, which is also called Verilog-1995

• “Verilog 2.0” is the IEEE Std. 1364-2001 Verilog standard, commonly called Verilog-2001; this generation of Verilog contains the first significant enhancements to Verilog since its release to the public in 1990

• “SystemVerilog 3.x” is Verilog-2001 plus an extensive set of high-level abstraction extensions, as defined in this document

• SystemVerilog 3.0, approved as an Accellera standard in June 2002, includes enhancements primarily directed at high-level architectural modeling

• SystemVerilog 3.1, approved as an Accellera standard in May 2003, includes enhancements primarily directed at advanced verification and C language integration

• SystemVerilog 3.1a, approved as an Accellera standard in April 2004, includes corrections and clarifications to the SystemVerilog 3.1 manual, as well as some additional enhancements to Verilog such as VCD and PLI specifications for SystemVerilog construct.

SystemVerilog is built on top of Verilog 2001. SystemVerilog improves the productivity, readability, and reusability of Verilog based code. The language enhancements in SystemVerilog provide more concise hardware Descriptions, while still providing an easy route with existing tools into current hardware implementation Flows. The enhancements also provide extensive support for directed and constrained-random testbench development, coverage driven verification, and assertion based verification.

SystemVerilog adds extended and new constructs to Verilog-2001, including:

• Extensions to data types for better encapsulation and compactness of code and for tighter specification

• C data types: int, typedef, struct, union, enum

• Other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety

• Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays including automatic memory management freeing users from de-allocation issues

• Dynamic casting and bit-stream casting

• Automatic/static specification on a per variable instance basis

• Extended operators for concise description

• Wild equality and inequality

• Built-in methods to extend the language

• Operator overloading

• streaming operators

• set membership

• Extended procedural statements

• Pattern matching on selection statements for use with tagged unions

• enhanced loop statements plus the foreach statement

• C like jump statements: return, break, continue

• Final blocks that executes at the end of simulation (inverse of initial)

• extended event control and sequence events

• Enhanced process control

• Extensions to always blocks to include synthesis consistent simulation semantics

• Extensions to fork…join to model pipelines and for enhanced process control

• Fine-grain process control

• Enhanced tasks and functions

• C like void functions

• pass by reference

• default arguments

• pass by name

• Optional arguments

• import/export functions for DPI (Direct Programming Interface)

• Classes: Object-Oriented mechanism that provides abstraction, encapsulation, and safe pointer capabilities

• Automated testbench support with random constraints

• Inter-process communication synchronization

• semaphores

• Mailboxes

• Event extensions, event variables, and event sequencing

• Clarification and extension of the scheduling semantics

• Cycle-Based Functionality: Clocking blocks and cycle-based attributes that help reduce development ease maintainability, and promote reusability:

• cycle-based signal drives and samples

• Synchronous samples

• race-free program context

• Assertion mechanism for verifying design intent and functional coverage intent.

• Property and sequence declarations

• Assertions and Coverage statements with action blocks

• Extended hierarchy support

• Packages for declaration encapsulation with import for controlled access

• compilation-unit scope nested modules and extern modules for separate compilation support

• Extension of port declarations to support interfaces, events, and variables.

• $root to provide unambiguous access using hierarchical references

• Interfaces to encapsulate communication and facilitate “Communication Oriented” design

• Functional coverage

• Direct Programming Interface (DPI) for clean, efficient interoperation with other languages (C provided)

• Assertion API

• Coverage API

• Data Read API

• VPI extensions for SystemVerilog constructs

• Concurrent assertion formal semantics